Electronic computer for addition and subtraction



Sept. 2, 1952 G. R. sTlBlTz 2,609,143

ELECTRONIC COMPUTER FDR ADDITION AND sBTRACTIoN Filed June 24. 1948 '7 Sheets-Sheet 1 Sept- 2, `1952 G. R. STIB-lTz 2,609,143

ELECTRONIC COMPUTER FOR ADDITION AND SUBTRACTION Filed June 24, 1948 7 Sheets-Sheet 2 4. /lgDuAL PULSE GENEAToR /55 giga INTEGRATUR AAAAA M6 23'50 INVHvToR.

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Vom-AGE A1356 (AOC') VoL-rAale A1556 (A se) OUTPUT (Inrexreo Vmrf) OuTPv'r 84 390 WAVE TMveL JNVENTOR.

LM., /LMM/fw ATTORNE 5 Patented Sept. 2, 1952 ELECTRONIC COMPUTER FOR ADDITION Y ANDSUBTRACTION.

George n. subicz, Burlington, vt. Application June a4, 194s, 'sei-iai No. 34,968

,. Y "44 claims'.- (Cl. zas-c1) The present` invention -relates to electronic digital computers and more particularly to a deupon such data and in spite of wide variations in vice ior performing the laddition or subtraction of binary numbers.

It is an object of the invention to provide an improved device for vadding and subtracting binary numbers at a rate oi' speed which is far in excess of present day commercial calculators.

It is another object of the invention to provide an improved sequential computer in which binary numbers are added by successive operation on each ordinal place with provision for automatically carrying a digit from one order to the next.y It is a more speciiic object to provide a computer which acts in turn on each of the digits comprising a binary number, and which includes a novel delay circuit which is synchronized to cause a carried digit to be precisely delayed until the instant of summation of digits Vin the next highest order. c

It is still another object to `provide an adding and subtracting device which is simple and inexpensive to construct, which is compact, and which may be advantageously utilized as a building block in the construction of computers for other mathematical operations.- such as multiplication and division. Neither the mechanical nor the electrical components need beconstructed with extreme precision and the electrical components are, for the most part, of the standard type used in radio receivers. The` number oi' tubes and other partsis small as compared to conventional computers of comparable speed; 'c

It is a further obiectLto provide an improved computer employing the binary system.y of numbers and utilizing devices having two stable conditions of operation in which the order ofthe two conditions or voltages to which the devices are subjected rather than any single instantaneous condition or voltage determines which of the-.two binary digits is represented. As a result the computer may be `made self-checking and of great accuracy in spite of relatively. wide variations in voltage. phasing andwave forminv the various portions oi the circuit and notwithstanding changes in the electrical characteristics of tubes and other component parts. K y i It is a related object to provide va novel delay and comparing circuit for sounding an alarm whenever one of the two conditions comprising a digit is lacking. j

It is a still further object to provide an improved means for the magnetic storage oiv information and a drive thereforV which enables synchronization not only betweenvarious problem data but alsowith controlu impulses acting driving speed. Y

It is an object to provide a computer of the sequential type whichis capable of performing addition operations upon'successive pairs of long binary numbers in rapid sequence without danger that a carry signal from the highest order in one sum will be'carried over to the lowest' order ofthe next sum. It is an allied object to provide a computer in which the complement of' a binary number may be readily` derived forl'purpos'es of subtraction and in? which the complement is so compensated that the difference obtained is absolutely accurate regardless oi the numberof binal places the device maybe equipped tohandle.

It is an aim of the invention in one of its aspects to provide an improved summing circuit including alternative embodiments thereof which is capable of producingwrite and carry voltages in response to voltages representative oi"` ,binary digits to be addevdgand in. accordance withl the rules governing binary addition. i

Other objects and advantages of theinvention will become apparentupon studying the following discussion and inspection oi thedrawings,v in which: l

Figure l is ablock diagram of a computer constructed in accordance with the present invention and suitable for adding or subtracting numbers stored in binary notation.

Fig. 2 is .a fragmentary' view of one of the storage-disks disclosed inFig. 1' and showing magnetic material distributed about the periphery thereof together with a cooperating recording or pickup head.` 1

Fig. 2a is similar to Fig. Z'but shows .the use of separate magnetic elementsfor storage purposes. -J

Fig. 3 is av fragmentary view 'showing the pulsing disk employed in Fig. 1.

Fig. 4 is a schematic diagram of a dual pulse generator controlledby the pulsing disk of Fig; 3.

Fig. 5 is a schematic diagram of a preferred integrator circuit employed herein;

. Fig. 6 shows a comparing and alarm circuit for detecting possible errors in the operation of the system of Fig. 1.

Fig. '7 shows a modified Hip-flop circuit employed in the present invention.

Fig. 8 shows a clamping and impedance changing circuit.

Fig. 9 shows a preferred form of phase inverter used to produce an inversion or ncomplementof the main data signals.v

-Figk 10 discloses a` summing circuit in accord- 3 ance with the present invention and employing three-element vacuum tubes.

Fig. a is a set of wave forms existing at various signicant points in the circuit of Fig. 10 and the system of Fig. 1.

Fig. 11 is an alternative summing circuit which differs from that` of Fig. 10 in that multi-gridI tubes are usegil. l i@ f5. g

Fig. lld'is'a set'of wave forms of the same general type as shown in* Fig. 10 but applicable to the circuit of Fig. 11.

Fig. 12 is another alternative-summing;circuit;v Fig. 12a is a set of wave forms for assistance in understanding the operation of the circuit of Fig. 12.

" ond condition as the first condition of a pair. In

Fig. 13 is a double pole single throw electronic ffm switch employed in the system for insertion Yof l digits in the lowest order. I

While the invention is susceptible of various modifications and alternative constructions-and usesl I have shown in'the drawings and will herein describe in detail only certain preferred embodiments yof the invention. It is to be'understood,` however, Athat I do not intend tolimit the inventionby suchdisclosure but aim to cover all modications'and alternative constructions and uses fallingwithinfthe spirit and scope of the :invention` as expressedfin the appended claims.-

,The computer ,to be described employs the binary system of numbers and itfwill be assumed that such-system is suiiiciently well knownytojany persons skilled in the computer artcasnnot to require discussion. Complete information on the binary system may berobtained from the various mathematical texts and texts concerning the theory of numbers.- Asis conventional, tlie'two binary digits employed will bereferred to as 0 izerolY and k1 (one)l in the discussion which follows.' 4` f l Yf Electronic 'computers employing binary num- 'bersare known'and have beenjuseful for calculating` trlajectorylancl for solving other lengthy mathematical problems. They have for the most part been relatively complicated and expensive, requiring so many vacuum tubes and related components and occupying so much space as to be completely unsuited. for usein the average business establishment. `Ars a result, problems involving payroll calculation, the solution ofv engineering design problems, and thelikerhaveibeenperformed either manually or byv theuseof'computers of themechanical or electromagnetic relay typeslv One of the reasons for the inherent complexity of prior art electronic computers is th'efmanner in which the terms making up a lengthy binary number'are treated. conventionally binary computers have used two-condition devices such as flip-nop circuits in which each term of a binary number is represented' by one of the two condi tions. Ihat is Vto say. representation of a lengthy binary number has required the use ofV a series of two-condition'devices.' one for 'each binary place. Since binary numbers have more than three times as many ordinal places as their decimal equivalents, the number of tubes required quickly reaches an impracticable level. Further, since tubes 'are subject to failure and erratic operation after extended periods of use. servicing is a difficult matter and it is almost impossible to obtain continued accuracy without resorting to elaborate checking schemes.

In the computer to be discussed two-condition devices are used to represent each digit with the order of Ithe two conditions determining which cruento simplify the description, this two-condin"tion v"representation of a digit will be referred to .as a couple or wave The terms plus-minus couple and "minus-plus couple" indicates the nature of the pulse. i. e., the direction of polarity change in pulses constituting a 1 and a 0 respectively'` on the main data leads. The two-condition couples may be stored in` a variety of forms without departing from the invention. I prefer to store the couples-magnetically;

One of the advantages of the manner of representing a digit as employed herein and as later covered in detail, is that it enables a simple and reliable check on each digit of the answer. Thus, if troublel develops at any point in the device which would'cause one of the two condition devicesito remain in one of 'its conditions; such fact is made'immed'iately apparent, whereas in more conventionab systems, failure of a single twocondition device simply produces an error in the answer without warning'that an error existed. Asfanadditional characteristic.' thedevice disclosed herein operates upon the terms of a binary number sequentially or'serially rather than stimultaneously. If it isv assumed, for example, that two" binary numbers are toV beF added,'the computer, a first-step. 'adds the terms `o'f"lowest order (normally the rst digit to the left of the binal point) progressing order by order to the highestterm in eachnumber. The lowest order digits 'of the two numbers are fed into a'summing circuit. The sum' of the two digits exists as a couple at the output of the summing'circuit, the couplev representing a digit 'which is then stored as the lowest order'digit of theanswer.' 'I'here also appears at the output of the summing circuit a carry signal in the form of a couple the nature of "which indicates whether a 1 or a 0 is to be carried to the' next highest order. The sum of the ydigits in `the next highest order is then obtained with 'the carry signal added thereto. The output of the summing circuit in the second operationv is likewise in'the form of a couple representing a digit whichV is recorded as the second term ofthe'answer together with a carry signal which isfadde'd tothe sum obtainedy in the thirdorder. The'summation of two binary numbers thus progresses until each term has been acted vupon andthe final answer is recorded. In thefevent thatsubtractmn rather than' addition is required, the-device incorporates provision for obtaining the complement of the subtr'ahend, which vis compensated` 'inf a particular manner, and thereafter perform-ing the process of addition as outlined above; 4

The invention-is also concerned" with a novel means for 'storing' the binary numbers to be operated upon and for recording the sum. Such storing means is of an improved form in which synchronization is substantially perfect not only as'between the various storage and recording components-but also with respect'tovthe electrical lcircuit components. .Further',l 'synchronized means are provided for delayed insertion of the barry signal obtained from the summation of the digits inflone" order; intov the sum o1!-V the `digits ofthe next Ahighest order. Delay circuits are employed inth'e latterwhich are unlockedv at preisel'yA synchronized intervals with respect to functions perfumed by the remaining compnents and under optimum input conditions so thatthere is substantially no possibility of error.

Prior yto discussing the' complete computer shown-in block form in Fig. l, it will be helpful .to consider-#the variouslsubcombinations into which lt may be conveniently divided.. Such subcom'binations include (a) .means for storing the binary numbers to be added -.or subtracted. (b) means for. deriving a data signal in theform `of couples of alternating polarity and for shaping the same. (c) meansincluding a summing circuit controlled by the couples and lproducing the answer in Lthe form of couples at the output thereof. (d) 'a delay circuit for "carrying from one order to the next. and (e) means for' storing the complete answer. Asancillary but none. the less .important features, provision is made for (f) producing timing or unlocking pulses, (g) for reversing the'couples comprising a number to be subtracted therebyobtainlng its complement and .(h) for eliminating. dimculties 'caused by the fugitive one arising in both addition and subtraction. -Finally there is provided. an alarm circuit (i) of novel and improved design for detectingv failureof the above portions oi' the device to perform their intended functions.

The diagram of Fig.l'has been simpliiled to facilitate understanding and bring out the operative .relationships between the various subcombinations. The circuit connections between the blocks are intended primarily. to show the routing of the control signals. Ground leadshave been eliminated and it will be assumed that means are provided for supplying appropriate anode and filament voltages to the vacuum tubes. Further, in the case of the blocks in Fig. 1, it will be understood that Vthe circuits. are disclosed from an operational standpoint and that circuit details may be'added lin a. practical embodiment in accordance with established radio and electronic practice. Wave forms are represented at the significant points in the circuit as traveling waves to' STORAGE oF BINARY NUMBERS For purposes of ready understanding of the system it will be assumed that the computer will be fed directly from binary storagedevices, such intelligence having previously been recorded thereon by 'any desired means. In the practice of the invention each binary term is stored in the form of a magnetized area made up of successive spots of magnetism having unlike polarity and forming what may be termed a. "magnetic couple. While it is possible to excite the computer by spotsf of magnetism on any movable magnetic element, it hasbeen found advantageous to-store the intelligence on rapidly rotating disks having a magnetizable periphery. l'tei'erring now to the block diagram of Fig. l. magnetic storage disks .2li and 2i are shown mounted on ashaft 22 which is rotated by a driving motor I4. .The disks .are preferably constructed as shownin Fig; 2 with a continuous strip 24 of retentive finely divided magnetic material bonded firmly totheV circular body..

Alternatively, thedisks 'may be madeas disclosed place about lthe periphery `by non-magnetic spacers or teeth 26B. In either embodiment. the disk body is preferably made of a non-magnetic material such as brass. In the case of the lalternate embodiment, the elements 25* may be formed of sintered slugs of magnetizable material pressed into place or may be built up by spraying, using metal spraying apparatus commercially available. If desired, the slots containing the magnetic material may be undercut as shown in order to hold such material firmlyv in place underhigh-speed conditions. l Y

The magnetic strip 24 may be magnetized by means of a recording head or armature 28 having a pair of coils 29, 30 mounted on a, C-shaped magnetic core 22. During recording of data the two coils 29, 3|) are preferably connected in the recording circuit in such a way that only one coil at a time will be energized. They are wound so that they tend to send ux in opposite directions around the magnetic circuit. Thus, as the disk 2l) rotates and the strip 24 passes adjacent the pole faces, the magnetic material is subjected to a magnetizing force in one direction or the other depending upon which coil is energized. This results in spots of magnetism which are retained until it is desired to read them oil'.

In the case of the alternate embodiment, the recording head designated 2lil is also C-shaped and is equipped with coils 29, 30, but since the head is differently oriented. the magnetic elements are magnetized in a direction parallel to the axis of rotation of the disk. In operation an adjacent pair of magnetic elements 25 is employed to represent one binary digit, the ilrst magnet of the pair having one polarity and the second magnet having the opposite polarity. In a practical embodiment it has been found convenient to store four binary numbers on a disk at one time. Assuming that yeach of such numbers is composed of up to twenty-five digits, two hundred individual magnets per disk are sumcient.

In reading the previously recorded numbers ofi the disk a pick-up head may be used which. is identical to the recording head 28 ory 2B, the coils being connected in series to increase the magnitude of the. voltage generated. vAs the magnetic spots pass adjacent thepole faces, they set up a. flux in the core generatingv a voltage in the V.coils which is proportional to the rate of change of this flux.

DEaIvI'NG AND sHAPING 0E PULSE COUPLES In order to excite the summing circuit to be later discussed. it is desirable that the signalobtained from the storage disks 20, 2l. be formed into a square wave voltage composed of couples of plus and minus pulses of alternating polarity corresponding tothe polarity of thevmagnets on the idisk. l.'

As a first step inobtaining the desired wave form,n the voltage generated in the head 28 is integrated to obtaina voltage which is proportional to uxand which,gat any instant, has a polarity which isrepresentativev of the polarity of the magnetic spotlying adjacent the pole faces at that instant. The integrator for accomplishing this is indicated generally at 32 in Fig. 1 and set forth in greater detail in Fig. 5. Referring to the iatteri figure itwill be seenthat the coil 29,

30 is connected to the grid "of a vacuum tube 34 Vhaving va capacitor 35 in shunt with the plate circuit thereof. 'I'he output of the tube' 34 vappears at the plate terminal 36, the tube being supplied from anysuitable high-voltage source through a load vresistor 31. The capacitor 35 in conjunction with `the tube resistance and load resistor 31 (which may be considered to be in parallel) serve as an RC integrator. The volt age across the capacitor is substantially the in tegral, with respect to time, of the voltage applied to the circuit, or'in this case-l the voltage generatedvin the pickup coils. Stated another way, the voltage is substantially proportional to flux in the disk. Sincethe pickup coils are not required to carry current, any inductance drop .thereinvis Ysubstantially eliminated and a high order of accuracy is achieved- V y Y As indicated at 38 (Fig. l) ,the wave atthe output lead 3813i the integrator consists of a series of direct and reversed cycles of substantially sinusoidal shape.- For convenience in `represent-,a-V tion the wave 38 may be thought of as traveling, here to the right, into the succeeding stages. This convention will be adhered to in all other wave representations towhich reference is made. Assuming that a minus-plus wave indicates the binary digit and assuming that a plus-minus impulse corresponds to the'binary digit '1, it will be seen that the Wave 38 at the output of the integrator represents the binary number 000110, being the electrical equivalent to the number recorded magnetically on the disk 20.

Meansl are next provided vfor deriving a supplementary signal which is the inversion of the main control signal. Such inverted signal is fed along with the main signal but on a separate lead through the succeeding stages. In the present instance this is accomplished by a vacuum tube amplier 39 which has a phase inverter stage to obtain push-pull output from `a single input signal. Since such an amplifier .may readily be constructed by one skilled in the art, it is not necessary to set forth the circuit indetail. Suffice it to say that the voltage wave existing at an output lead 40 will be the same as that existing at the input lead 36 except greater in magnitude while the` voltage on a second output lead 4| is` the inverted image thereof.

To convert the sine wave couples te square wave couples and to obtain a uniform properly synchronized voltage wave for all digits regardless of the magnitude of the signal obtained from the disk, a ilip-op ldevice l42 having .provision for periodic unlocking is employed. The circuit of the latter is set forth in Fig. 7 where it will be seen that it includes two triodes 44, 45 which may be included within the same envelope, if desired. Such triodes include cathodes 44B, 45a; grids 44h, 45h; and plates 44, 45., respectively. 'Ihe circuit is arranged so that there are two stabie conditions of operation: (a) with the grid 44h at zero potential and with `grid 45h below cutoff, and (b.) `witlith'e vgrid '45h at zero potential and grid 44J below cutoil.` To this end the grids and platesare `cross-connected by resistors 46, 40 and 4respectively grounded through grid resistors 49, 50 and bias source 53. The triodes are fed respectively through plate resisters I, 52 from a high'voltage source ,54. The output of the flip-flopcircuit'istaken directly from vthe plates via output leads 55, 56;

When the first stable vcondition (a) exists, the triode 44 conducts and draws plate current from source 54rthrough resistor 51. This .produces a voltage drop across the resistor 5I which decreases the potential of the output vlead 55 rela-s tive to ground. Y Similarly, when the second conditionib) exists, triode 45 conducts to decrease the potentialof the output lead 56 relative to ground. When the. flip-flop circuit is in one of its stable conditions, itwill remain in that condition 'due to the above-mentioned cross connection.g x.Thus. if triode45 is non-conducting, the potentialof its vplate will be high and due to its connection with the grid of triode 44 (through resisixir 48) it will maintain the potential of that grido-n the positive side, of cut-off and cause the latter tube to 'conduct heavily. Conversely. if "triode 45=is conducting, itwill maintain the gridof triade 44 beyond cut-o for the full range of 'voltages 'on input ylead 40. To cause the flipo'p circuit'to Iremain locked in one condition, the output 4of Athe,amplifier-inverter 39 'is limitedto'a moderate level.

-Inmrder toena'ble the ilip-iiop circuit to be converted from one stable condition to another. means are provided for unlocking the tubes, Le., for renderingfboth tubes momentarily non-conductingn'his: is preferably accomplished by cormectingcathodes 44a, 45e, by a line 58, to a source generating positive pulses synchronized withthesignals received at the input leads 40, 4|. The means vfor generating such pulses will be referred to in detailL at a later point. Suflice it vto say that a positive pulse applied to the cathodes makes both tubes non-conducting, and when such Voltage is removed the tube which starts conducting will be determined by the then existing voltage at the input terminals. The output voltage'is independent of the input under normal locked vconditions but may be considered to aline itself with 'the input voltage which obtains 'during the instant that the circuit is unlocked. It'willbe apparent to one skilled in the art 'that' the` kpresent invention is not limited to the useofip-llo'p circuits 42 having a pair, of input leads and the circuit may be operated successively with one of the input leads eliminated. cessful with ine of 'the input condtions would The 4opposite grid under such conditions would receive its voltage only from the plate of the first tube.

Referring again to Fig. l., it will be seen that the output signal from the flip-nop circuit 42 consists of a train of square waves 60 on lead 55 with their inverted counterparts 6I on lead 56. As stated above, allof the units in the block diagram have a common ground connection and it is therefore desirable that the signal voltage bear a predetermined relationship to ground potential. Itis lfurther desirable that the source be c'hangedgfroin high impedance lto one o f relatively low impedance for feeding into the summing portion of the device to be discussed. Accordingly, the .dual signal is fed into a clamp and impedance Vchanger 62, the circuit of which isset forth in detail in Fig. 8. This device includes a double emessi, sa 'and a double mode ss, 68; The diode circuits include input capacitors 69, 10 which arein effect, shuntedk to ground -through plate resistors A1|-.'2. It will be apparent, therefore, that the diodefcircuits serve as conventional.

clamping-devices, maintaining thepositive portions of theinput signals at a positive potential determined by battery 13. 'I'he triodes 66, 68 are excited 'by the outputs of the clamping circuits and includecathode resistors 14, 1.5 across which the output is taken on leads 16, 18. The latter' tubes thus servel 'as conventional vcathode In order to insert a carry signal from .the pre'- Fig. 1 directly below that previously discussedv and corresponding primed reference numerals have been employed to indicate that the compo-.2

nents are equivalent. Square output waves 19. 80 are also obtained for feeding' into the'summing circuit.

Included within the first channel is a reversing switch8| which. as will later appear, is employed 'ing subtraction and'whichv for present purposes may be disregarded.

` l A: ..-DrGrI1.aDDERjcmcUrT Ih apparatus'thusffar described has beenfor theprpos'e oi' obtaining' reliable and accurately phased square lwave couples representative of a binaryfhumberf'The purpose of the digit adder circuit indicated ,generally at 82 (Fig. 1) is to utilie such voltage couplesto produce a sequence ofcouples on' each oi' twooutput leads, one se- 'quenefrpresenting the answer of the summa'- tion;I 'and the other sequence representing a series of'digits. 'The adder .portion of the apparatus to be discussed-utilizes three input voltages Yaridl'tleir inverted counterparts, the first two of suchiyltages being supplied from the channels 'controlled by tneaisks 20,521; It" w111 be found v convenient to designate the-main output wave oi the rs'tchannelas A, itsinversion as A' and the output ot the second channel as B having an inversion B.

In practicing the invention three alternative circuits are provided asset forth in' Figs. 10,` l1

' and 12 to act upon two simultaneously received input couples in a predetermined manner which satisiles the requirements oi binary addition as the same is carried out order by order. Thus, if oneoi the input signals represents a binary 1, and the other0,V `the summing circuit should write 1 and nothing should be carried over to the next higher order'. IfI both of the inputs A (and its inversion A') and B (with its inversion B) carry acouple representative of a binary digit 1 the'SumJmingcix-cuit should write a 0 and carry viou'sly summed' order, a 'third inputy C having an inversion 'C'is employed. The couple fed to ,the'summing circuit at C, C' is supplied from a novel delay' circuit to whichjmore detailed reference Willlaterbemade.' Suillce it to say that the 4carrysignal,always arrivestat the input oi' the .summing circuit just one order' or cycle delayed or late. {I'hus'all three oi' inputs A,`A; B, B; and'C. Cf'mayat any instant be carrying a couple corresponding "to a binary 0 or a. binary 1. `It will be apparent, then,`that when all three inputs are a ,binary 1, both outputs should be a binary 1 f 'By this point in the discussion it will be clear that, the function of the adder circuits, for examplethat shown in Fig. l0, is to respond to the flo grouped respectively'A, B, C, and AUB', C. The output leads include a write lead 84 and a carry lead 85. 'It will be understood hat the word write is usedln a broad sense to indicate that the outputsignal on lead 84 is recorded as of the sum. Preferably such recording is accomplished magnetically as will later appear. The actual printing of the information is not specifically covered in the present application.

The adder circuit as disclosed in Fig. 10 includes six valves inthe form of triodes, adjacent v ones of which are includedfwithin thesame glass envelope. Such triodes are designated by the numerals 86-8I. Thecathodes, gridsfand plates oi' each of the triodes carry the corresponding numeral with the respective subscript a, b, orc. Referring in greater detail to the input portion of the adder circuit 82 it will be seen thatr the leads Af, B',` C' are all conneced to the control grid of the tube 81 through grid resistors` 192,88, 944. Similarly, the input leads A, B, C, are con'- nected to the grids 'oi the triodes 88.801 through kgrid resistors' ss. as', s1 and 58,99, loo. nach or thejtriodes 81--88 includes a source'oibias comprising a grid resistorandj grid battery which have been ,designated respectively `bythe numerals |0I, |02;V |03, |04; and |08, |06.,1The

plates oi` the triodes Bul-'88 are connected to'a l source oi high voltage |08 via dropping 'resistors |09, ||0, III. vBecause of the gridA connections and the plate dropping resistors, the voltages existing at the plate terminals ||2, |13, v| I4 swing through relatively wide limits determined .by the signal voltages existing at the input. The tubes 8T-89 may thus-be 'conveniently referred tov a primary" control or input tubes. .y

In accordancewith one'of the aspects or' the invention, the plate potentials' of the primary control tubes existing at terminals ||2, H3, v|14 are' applied through grid resistors to the grid 90b ofv a secondaryy control tube 90. Such resistors are designated'. H5, H6, ||1 respectively. The grid 90b is further connected to a source of bias including .a resistor I8 'and a battery or the like ||9. On the' plate sidefa dro'ppingresistor |24 permits the 'plate 'terminal'yoltage toswing over relatively wide limits. d S

Through the action of the circuit'thus far discussed, the voltages existing at the input leads are employed inY combination, to control the'co'n'- ductivity of the primary control tubes 81,-89 While the resulting states] of conductivity" act jointly to controljthe' vconductivityin the secondaryjcontrolltube 90 and the voltage at `its 'output terminal |25.' As shown in Fig. 10, .the'prif man' control tube 81 serves to controlthe coni- 'ductivity in a carry output tube designated at8|i `of conductivity O .f 'such'output tubes in turn de# termines the'instantaneouspotential on the write vand carry output leads. Completing the circuit, it will be lnoted that the output tubes have associated grid resistors |22, |23 and cathode resistors |20, |2| respectively,'causing the stages to func.- tion as lowlimpedance cathode followers., Y 'In practicingthe invention the bias on the. grid lof the primary' control tube Slis of sucha value that it'maintain's the grid of triode 8l belowY cutofi` unless two or more of the three leads A', B', C are positive. Since the inverse voltages appear' at the input leads `A,. B, C, this'V is equivalent vto saying that the triode 8l'is .maintained beyond cut-oil unless oneor nonejofthe .leads- A,'.,B,C are positive. In. order vthattheei'lect vofsuch 11 bias condition maygbenscertained .at a glance.

.the following'"liable-Jlrhas been prepared, listing i2 positive at :the .beginning of a digit space. It is apparent thatthis Iullls one of the conditions ccf binary addition, namely, a binary lcmust be written only when the total of the numbers added .is 1.01` 3.v 1

Allt nrst glance it might appear that the volt- For oi' co'nvenience.Zl been used to dosignatethefact thfat'aparticular grid is `at zero potentiall (corresponding `to .of plate current)` while v has been employed to designate the fact that a given lgrld is biased` beyond cutoitherebyto' preventthe .owot plate current. In a practical circuit using' conventional receiving-type' triodes it has beeniond that a plate ,swing of from to 105` volts is yreadily obtained between the conducting and non cnducting conditions respectively( VThese values have accordingly been'used in the table'as representative.

, In utilizing Table I it will be seen in the case of; primary control. triode B1 thatv the grid bias vis zero .and the plate' voltage correspondingly low with nne or one of .the leads A, B, C positive; While the triodeiscut-oi'i and the plate voltage correspondingly whenQ eitlieitwo or three of the leads A, B, C are positive.

Turning attention now to the control triode la, the bias derived from the source |04 is so adjusted that a positive voltage at any one of the leads A, B, C, is sun'icient to cause the ltube to conduct. When nonevof the leads A, B, C is positive, such tube is non-conducting and the platelterminal voltage `is correspondingly high.

In the case of the primary control triode 89 the voltage/ofthe associated grid' 'battery |06 is .of Vsuch value that all three ci the leadsA, B, C must be positive forconduction .to take. place. With less than three leads' positive the tube is nonconducting, and theplate voltage is high.

The function oi' the secondary control tube `Bil diners from that 'of the control tubes previously discussed in that .the grid B0 is controlled not by theinput voltages directly but by the state-of conductivity 0f the primary control tubes. To obtain the'desiredoutput'signal the triode 90 has its bias set by the battery Il 9 so that the tube is cutoff until two o1' the three leads supplying the grid network become appreciably positive. This is equivalent to saying that the secondary control tubeV 90 is cut-oil' unless at least two of the primary control triodes are cut-off` and, therefore, non-corniucting. From inspection of the table, it is apparent that the secondary control triode will conduct only when none of the input leads A, B, C'are positive or when two of such leads vare positive.4 Under conditions in which either joneor three ofthe leads A, B, C are positive; the triode. 90 is biased to cuteoilv and, therefore, nonhconducting. The write output tube 9i is arranged to apply a positive voltage to the write output lead 84v only when the secondary control tube 9|! is non-conducting. Thus a write l s Signal will exist at the output lead 84 onlyunder two conditions: When one of the leads A. B, C is positive or when three of the leads A. B. C al agesonthe input leads would have very little individual eiect dueto the paralleling `of the grid resistors i12-94, 95-.91,-and 98-IOIl respectively. It has been found as a practicalrmatter that the arrangementsho'wn causes'the grid voltage vto existin desired welldened steps and circuit eomplications encountered in anyattempt to add-the input voltages serially are avoided. 1

Referring, now tothe carry output Jtube 86;( at the left-hand portionuof 10) itwill be seen that .armati-ve' rvoltage-Will be .applied tosthe carryoutputlead 85A only when the primary control tube 81 is out on. As will be-apparent from the first columnoiv the table a positivesignaljis produced at the carry output ,lead only when two or three ofthe input-leads Ai/B, C are positive. Thus a carry l signal will Ybe obtained onlylwhen two lor three of the input leads A, B,'C are positive for the first half of the cycle. This fulfills the second requirement for binary addition, namely, carrying V(tol the next highest order) whenever the binary sum exceeds 1. In short, the circuit of Fig. 10 satisfies the requirements for sequential binaryA addition except for delaying the carry signal until the next highest order is being summed. y

DELAY GIRCUIT In the preceding section it hasbeenassumed that the appropriate-carry signal derived from the summationin a previous order has been appropriatelydelayed so that it may be added tothe signals existing at. the A, A', and B, B'input leads. ItV has further been Jassumed that the carry signal appearing at the carry output lead 8 5 is suitably delayed toappear at the leads C, C' upon summing the signals corresponding to the binary digits of the next higher order. In accordance With the present invention, novel means ar'e provided between the output'lead B5 and the input lead C, C' for delaying thesignalover a space of time cor'- responding to onefcouple, in other Words, for one summing cycle... This is` accomplished by 'providing aseries vofiiip-.ilop circuits which are suc- VcessivelyV unlocked by pulses generated in aecurately timed synchromzationwith respect to the stored data. As .employedin the preferred embodiment illustrated in 1 the flip-flop circuits are of the same type previously discussed in connection' with circuits 42 and 42 and set forth in detail in Fig.`7. It will be recalled that a positive pulse appliedto the cathodes serves to unlock thecircuit vthereby enabling it to respond to the then existing voltage at its input terminals.

Prior yto being fed through the flip-nop devices the signalen thecarry lead is inverted by meansof a phase inverter |30. The specii-lc cir.-

:uit as set. forth in.1',ig.9'willibefseen to be of more or less conventional design including a pair 3f triodes |3I, |32 having cathodes, grids and :ilates carrying; corresponding subscripts 11,1, c. Ihe grid |3|h of the triode |3'| is excited directly from the line 8.5 tov produce a correspondingout'- put signal on an output lead |34. The grid of the triode |32 is oppositely excited by'a diagonally-connected resistor |35 and series capacitor |30 leading to thev plate of the first triode. It willA be apparent to one skilled inV the art that a positive voltage applied to they gridA of the first triode |3| will cause a corresponding negative voltage to be applied to the grid of the second triode |32. Asaresult the voltage appearingnat the secondv output lead |33 will be.- opposite in phasing to the voltage appearing atA the, output lead |34 as shown. by the. typical WavesY |39.; |40.

From this point the carry signal passes through four serially arrangedflip-op circuits |,4|,y |42,V |43, |44.y Those circuits. are, in general, unlocked` individually and inregularly recurring sequence to pass the information down the line one step at a. time. Preferably the flip-flop devices are arrangedin, two alternating groupsv |4| |43 and |42, |44 and unlocking pulses are fed to theg-,roups alternately. In the present instance thepulses are supplied to nip-flop circuits Uil,` |43 through an unlocking lead |45 and are supplied'` to flipop devices |42, |44 through an unlocking pulse lead |46 at a rate of two pulses per cycle, Such pulses are furthermore timed With the data fed into the summing circuit to insure that a complete unlocking cycle occurs which is synchronized with successive cycles of data. Specifically, at the start of a cycle comprising one Waveor couple, the flip-flop circuits |42, |44 are first unlocked. This feeds 'into the summing circuit the carry signal from the previous summation. One-quarter of a cycle later the flip-flop circuits |4|, |43 are unlocked sothat |4| may respond t the then existing output of the `summing circuit; In a similar fashion the flip-flop circuits |'42` and |43 are; unlocked at the middle andv threequarter points of the cycle respectively; At the start ofA the-next cycle, the signal then existingat the output oi' the flip-flop circuit |44 is applied to the inputleads C, C', such signalscorrespond.- ing exactly to the carry signal which appeared at the carry lead 85 just one cycle before.

From the foregoing it is seen that the four serially connected flip-flop circuits |4||44 are unlocked successively at quarter cycle intervals to provide a complete cycle or digit space delay for the carry signal. In addition, the specic delay arrangementr enables a maximum amount of reliability sinceY it operates substantially independently ofi the. Wave. form andy in spitey of rela.- tively wide variationsy in the amplitude of the wave. In this connection note, that the rst flipflop circuit, which is., the most critical. since, it determines the signal to be passed along by the remainder ofthe flip-flop. circuits, isunlocked at the first and third quarter points of a couple.. These points are approximately centered within the regions of maximum amplitude. rlhus, if the magnitude of the wave should decrease for any reason, posi-tive response of the rst flip-flop circuit isstill assured. Opera-tion is likewise reliable in spite ofv considerable inaccuracy in the phasing of the data signal and in spite of sloping or rounding oi of the wave front. In short, the circuits are kept` synchronized by the unlocking pulses so that construction of the computer as a whole isnot unduly critical.

In summarizing, it; will be, apparent that, the cir-y cuit; loop.Y startingy at; lead; 8.5 andA ending at. leads C'. Ctservesto; transport aV carry signal from. one

- order to. thenextiiand; may be thought of asia feed-back; circuitf., with` a. single cycle; (or` digit) delay.

GENERATION. OF UNLOCKING PULSES Reference will next bermade toA theV preferred means for: applying` pulses.. tov theleads |45, |546 for unlocking; nip-flop circuits- |4||44. To. insurasynchronism the unlocking pulses; preferably originate;rr in a pulsing;l diskA |50v which is shown, in, thev upper left-hand corner oi` Eig. l, and mounted: on the` shaftA 22 which. drives the storage disks 20, 2| previously referred to. As shown in Fig.- 3, the disk |50 has on its periphery a plurality of' closely spaced teeth |5| which cooperate,- with a. pickup coil` |52- having a c ore |54. Tliejcore. preferably has a chiselvshaped tip which extends-within; ashortA distance (about .0|l5 inch). of the crests ofA the teeth |5|. A direct current irs-passed through the coil |52 andas the: teethL on the rortatingY disk pass beneath the core, the-v reluctance ofthe. magnetic circuit is, changed, inducing, an. alternating' voltage |53y in the coil which is then; peaked, inverted, and amplified. The devicefor accomplishing the latter is termed the. dualA pulse generator |55, the preferred circuitbelng disclosed in detail in Fig. 4,to.which reference is nowA made.

As shown, the, pulse generator includes a, pair ofcascaded amplifying tubes |56,Y |58, the signal froml the pickup coil |52 being conveyed to the grid of the first. tube through a capacitor |59. The ampliiied signal from the tube |58 is then passed through the primary ofl asaturable transformer having' a center tapped secondary Iil". Due to, saturation a voltage isl obtained atA each side of the center tap which is very peaked. Such voltages, oppositely phased, are separately amplified byampliiiers indicated at |63. |64v respectively; 'I'he latter serve to excite respective cathode follower stages |66 which supply the output leads |45, |46 previously referred to. For purposes of clarity the peaked unlocking Waves on the leads |45, |46 are shown in Fig- 1 as: |60, |69, the pulses occurring at: the rate oiv twoY on each lineY per cycle.Y WhileA each ofl the; lines. |45, |46 carries only two unlockingpulses per cycle, itis to be. noted` that the pulses supplied on one line alternate with thosein the other; so that a total of four unlocking pulses per cycle are suppliedy to. the` delay. channel as a whole.

Sincey the pulsing disk |50. is rigidly coupled for. rotation. with the data disks 20V and 2|, the unlocking pulses will be in sten with the data signals. The angular relationship between the datadisks20, 2| and the pulsingdisk |50 is not depended upon, however, for exact synchroniza-- tion between the data signals and the unlocking of the delaycircuit. O-n the contrary it will be noted that the data flip-flop devices 42, 42' are unlocked `by the same set of. pulse leadswhich tion is positive and the assembling of the disksk on the shaft 22 need not be a high precision operation.- To insure that the delayed carry signal is fed into the summing circuit in step with the incoming data, still another precaution is taken. This has to do with the timing of the unlocking pulses in the delay circuit relative to the wave form of the signal being acted upon. As pointed out above, the unlocking pulses are applied to the flrst flip-dop circuit |4| near the center of each half of the input wave or couple. Since the wave is substantially rectangular, it will be apparent that considerable departure on one side or the other of the center point may be tolerated without causing misphasing rdiiilculties.

While the preferred circuit includes four serial ip-iiop devices unlocked with four pulses per cycle, it will be appreciated by one skilled in the art that a greater number could be used if desired without departing from the present teachings, always -keeping in mind that the number of unlocking pulses should be sufilcientto cause a delay of exactly one cycle or digit space.

RECORDING OF WRITE SIGNAL As previously stated, the signal appearing on the write lead 84 consists of a successi-on of couples of the s-ame general wave form as those applied at the input of the summing circuit, the wave form being shown at (Fig. 1) for purposes of convenience. The signal is then preferably passed through a phase inverter appearing in both the direct and inverted form at leads ||-2, IM.A At this point an alarm circuit may be employed to which detailed reference will later be made. The direct and inverted waves |82, |84 are next amplified by any suitable amplifler |18. The output of the amplifier is then passed through the coils of a recorder head at |11 to record the sum magnetically on an output disk |80. The latter is preferably of the same type as the storage disks 20, 2| and is synchronized therewith by mounting on the same shaft 22. The recorder head m-ay likewise be of the same type discussed in detail in connection with Fig. 2. The individual coils 29, 30 thereof being supplied through the'leads |18, |19. The recorded data corresponding to the binary sum of the binary numbers appearing on the disks 20, 2| may then be read-off of the disk |'80 by any suitable pickup head (not shown). When the -adder is employed as part of a more complete computer capable of multiplying and the like, additional numbers may be continuously recorded on the disks 20, 2| and their sums only temporarily stored on thel disk |80. The present device is thus seen to be eminently well suited for continuous high speed operation.

While it is true that the signals |82, |80 to be written are square waves, it has been observed that the resulting magnetism impressed on the dis-k |80 is more nearly sinusoidal. This is believed due to the fact that a certain amount of neutralization or averaging of the flux takes place on the disk at the boundaries between the uxes of opposite sign. In any event the signal subsequently picked up from the output disk |80 as the answer is read will be found to be substantially of the' same wave form as that read from the input disks 20, 2 I.

16 ESUINIMARY OF OPERATION .AND WAVE FORMS While the complete computer contains additional meritorious features requiring discussion. it will be found convenient to review the operation of the components thus far discussed in order to show more clearly the manner in which the information picked up from the storage disks 20, 2| is recorded as a binary sum on the output disks |80. Turning to Fig. 10a, the Wave forms of the signal as they exist at a number of signincant points in the circuit are shown and may be conveniently grouped as follows:

Pulse output #l from dual pulse generator |55 Pulse output #2 from dual pulse generator |55 Signal from rst storage disk 20 Signal from first storage disk after squaring and clamping (lead A to summing circuit) 'Signal from second storage disk 2| Signal from second storage disk after squaring and clamping (lead B to summing circuit) Delayed carry signal after clamping (lead C to summing circuit) Plate voltage of triode '8l (carry signal before delay) Plate voltage of triode 88 Plate voltage of triode 89 Plate voltage of triode 90 (write signal as applied to recording coil) All of the waves have been vertically alined with respect to a common time axis so that it is possible to trace the effect of digit couples fed into the circuit from the storage disks 20. 2| from beginning to end. Since the Waves may be considered as flowing progressively to the right, the first digit space or order is along the righthand edge of Fig. 10a and has been designated a. The couples corresponding to digits in the next highest order operated upon in the computer occupy a space b. ySuccessive orders have been designated as c, d, e, and f. Individual couples are denoted by a corresponding subscript.

The over-all operation of the computer may be understood by observing what occurs during solution of a practical problem: the addition of 000110 to 000011 previously recorded and stored on disks 20, 2|. Both of these numbers together with their sum, 001001. are placed in Fig. 10a immediately below the couples which represent them. As a rst step the first (lowest order) digit read off of the storage disk 20 is 0 (zero). The couple corresponding to this first digit signal has been designated 38a in Fig. 10a, and after shaping and clamping produces a square minusplus couple 19xl which is fed into the summing circuit on lead A. The lowest order digit of the second binary number is 1 (one) and appears in magnetic form on the second storage disk 2|. The electrical couple corresponding thereto is designated 38', which after shaping and clamping appears as the plus-minus couple 19's on lead B.

It will be assumed that the carry signal C is 0, the first couple of the carry signal being minus-plus and indicated at H1B.

Under the above conditions the only one of the signals A, B, C having an initial positive portion is B. The resulting voltages appearing at the plates of the triodes 8T-90 may be determined merely upon inspection of the previously discussed Table I. These voltage waves are Vrepresented in the drawing as |26|29 with the th Wave 011 the Write Output-lead BIL Which S' amplified'. and recorded. 'asiel (one) on. the out# pnt disk |88:

- The carry signal is 'dependent the 'out-A put voltage of'ftrldfe 81.' Sinc'the SumI for the met 'order (as seen above.) is 1, the carrys'ignal is.` '0 (aero) as yrepre'seiritecl by the. minus-plus ocio-ple |23.

b as the minus-plus couple Il!n on. input lea'dG;

Having observed the sequence of operations in the iirst order e, attention is next directed to the second. column .from the. 4right in Fig.. 10a which` shows thev operation ot I the computer during thesecond orderb. In thesecond orderthe digit on each of the' storage disks 2l), .isTv

1 (one). Thisy resultsin the applicationof the. pliisffrxiiniis'pulses19"4 and 19's to. the summing input leads A. and B respectively. The voltage variation at the plate of tube 9D constitutes a. minus-plus` couple i291 which is fed at low imf pedancel toA the write leaded. is thereupon written, magnetically on the output diskV` |80.

The voltegefvariation at the plate oftube 81 on. theother handduringthis cycle isaplus-minusy Couple IZlilP-- This. corresponds to carrying a.

binary 1 to the. next order. After delayit w'i11 be seenthatthis carry signal isfed into the sum mingycircuit at C; inthe next-higher order c.. Thel above process is repeated for the ordersc.. d., ey and f resultingin thewriting of ,digits 0.1

0 and 0 on thedisk I8|I` to completethefanswer. namely. 00.17001..r 4

While a sixA digit binary problem has been taken as representative,y a practical computer employing the present teachings is `not solita-- item. Computers may. be` readily constructed with a capacity of 25 orA more binalplaces which.

takes careof thegreat ,majority of problems arisinginl business.4 When using aY machine ofA larger capacity for a relatively simple. problemi.

suchas that outlinedabove, the higherV orders on the disks 20, 2i should be completely occupied by zeros and corresponding zeros. willY thus be written inthe. higher. orders of. the.- answer on;

disk IBII.V LGW ORDER DIGIT'INSERTE'R POR CARRY CIRCUIT' In the above discussion it has beenv 'assumed that the initial information fed from the carry delay circuit representeda binary digit .(ls'othall',

in effect, there was nothing carried in summing the digits of the first order. Ifthe computer were usedto perform but a single problem of additio'mlthis would4 in general he true. HoW- ever, since 'the computer is normally. called. upon'v to perform a large number of problems ofaddi.- tion in quicksuccession, the addition ofthe first digits of a given pair of numbers follows directly after the addition of the l'ast digits of the pre*- cedin'g number. VIt is, thereforeouite possible that the carry for the first digits added might not'` alwaysA be zeroV asit should' to obtain the correct answer. In accordance with 'one-fofth'f'aV aspects 'of the invention, therefore, means are. included in the carry circuit for disabling the carry circuit during the addition ofthe rst digit and inserting a zero signal (minus-plus couple) Because of the deliay circuit this carry 'signal' isl carlried over into the order;

the carry. delay-circuit.

118 in. the inptx-leads G, 'Cf-a. Preferahlyfn is accomplished. by.- `a simple switching arrange-l ment which causes. a. minus-plus. couple he. appliedl during the.` summation ot; digitsin rstorders 'andithe carry. toY normally. during. the remainder. of the number..

Prior tov'az. discussion 'ofy the manneirin'. the initial: 'zero signal isv inserted in leadsy itv will `be. helpful to. refer to. that. of the apparatus. used.. for. Vgenerating imserted. zero.V AfsV disclosed. 1. a geni-- eratinrg disk 2020 employed which. on shaftza isv rotated. in synchronism the storage. gears 2D, 21. The disk. 20w structe'df substantially. the same. as; disklinz einY cept. that. the pitch. of. the tethi onudisklt Aix twice the 'pitchof the Fteeth on. disk |50; -Adirect's currentispassed through the pick-up c'oii ma which issimiiar tofcoil: 1:52. Asthemeluo'taieem. the. magnetic circuitv is changed. by.' the. ment of the teeth past the tip of the cones.. alternating. voltage representativeof a. see's'vof binary Us is produoedas indicated..at uli.. signalf is .then amplified ina vacuum. tube fier ZMwhich isconventi'onal in design..

Next, the` waive issnaped. and inverted by ing -iti through a fiipaflopdevioe 204i out` put. leadsztli, 2M and an: unlockingy lead,l mi. Such4 iiipflopp device is equivalent .to ,the-.devices 421,42 andfshowln in detailirrEig; 7.1 Th'eshapedl output signal 2M. and its'ihversonlil axenfext; fe'dzthrough aA reversing switchlI-i havingotput; leads llt; 211., The reversing switch. may'abe'. passed over f'o'rthe, present since it is.. not. nora 5 many-employed inthe process-of .simpleradditpm SubsecwentlyY the signall passes through axdbui.

pole singlel throw switch 2| 5'. which: is: identical@ to the single throw.` switch M81 previously.: mi ferredto-'and which is contained at the :output'o It.` will be f apparent.timel with the switch M8 closedi'an'dlwiththe'swih. 2i .fi-open, zerosirom the zerogenerating .diskxlli will', be blocked; oir. and the circuitrwill. operato; inthe manner previously' described.. Hott/eilen; withthereverse condition existin'gVthat isfwith.,

the switch llt in fthe-carry. delay with the switch 2I5 from the zero:.generatfmam` disk 2ll0closed: a. constant; stream'. .of 'couples representa-tive of binary. @fs 'will inputleads:C,.C, ofv thesummin'g circuiti. But: as pointed outabo've, it-is 'desirable vthat a'V be fed'into the carry" input: .leads C, C? .onlyA ingftile -flrst*cyc1e oRd-igt Space.

Accordingly., means are providcdirorcperating:

thsswitch 2.1 5f in sucnsmanner martha is ciosedfonly during the` nrstdigit spaceora.

summation. In the-present instance-this-'is complished by a switch controlf disk @2U teeth or 4f'ec'l'ilivalent magnetic-irregularities 2H at* spaced intervals about tnepenpneiythereef'and corresponding in positioningl to the f'aegir'mingoi' theebinar-y numbers on thestra'gediSks 2i, 24J A piek-up head 223` cooperates with the diskfn order digits ofthe twobii'i'ary numbers Vfeci" ffioirl:L

the storage disks zo, 2|. 'rhs amplifier @tout is used to excite la ii'ipfi-opdevice 226. havin'gi'output leads 228, 22llA andr of 'the same gener'a'lftyie: previously discussed inconnection with. 'Figfli' Theumockin'g pulses for the device-iffare-'cs-f tained from an auxiliary disk 230 having magnetic irregularities thereon and fitted with a cooperating pick-up head just as in the case of disk 220. To steepen and amplify the wave front, thepulses are fed through a peaking amplifier 23| of a type well known to those skilled in the art before being applied to the pulse lead 224 of theip-ilop circuit. As shown, disks 220, 230 preferably carry the peripheral teeth in groups of two with the first producing .a control pulse at the very beginning and the second producing a controlpulse near the end of the rst binary digit space. The rst pulses are effective. to change the dip-flop device 226 to its alternate or switched condition and the other to restore it to its normal condition. The output of the iipop device is then applied to the switches |40 and 2|5 so that 2|5 conducts only during the first digit space and |48 conducts only during the remainder of the spaces comprising a binary number.

While a number of different switch circuits may be used to perform the above-outlined function without departing from the invention, the preferred form of electronic switch is disclosed in detail in Fig. 13. The circuit includes four triodes 250, 25|, 252. 253, having cathodes, grids, and plates bearing corresponding reference numerals with the subscript a, b, or c respectively. In the plate circuits of the triodes 25|, 253 are included plate dropping resistors 255, 256 respectively. The cathodes are connected together in pairs and are grounded through cathode resistors 259. 259. Referring to the left-hand portion of the circuit, it can be seen that if the grid 252b has a relatively large potential applied to it, current will flow through `a circuit including thecathode resistor 259, cathode 252a and plate 2 52 thus producing a relatively large voltage drop across the cathode resistor. This raises the cathode vpotential sufficiently to bias the triode 253 to cut-off for al1 values of voltage normally applied to the input lead 2li. Thus normal variations in the signal voltage applied to the input lead 2|6 cannot affect the current through plate resistor 256 and the potential at plate 253c thus remains xed.

' If now the voltage applied to the grid 252b by the control lead 229 is materially reduced, the current drawn by the triode 252 is also materially reduced. The eifect of the latter is to lower the potential of the cathode 253 to the point where voltage swings applied to the grid 253D by theinput lead 2|6 will cause corresponding variations 1n the plate current. These plate current variations will result in a varying voltage drop across the plate resistor 250 and the input signal will be reproduced at the output lead 2|9. Inherent in the latter operation is a 180 phase reversal. The latter may, however, be readily compensated for merely by interchanging the two output leads 2|9, 2|9, such cross connection being set forth in the circuit shown in Fig. 13. From the foregoing it is evident that with a negative potential applied to the pulse lead 229 the switch is effectively closed, that is, the output voltage corresponds to the then existing value of the input voltage. Conversely, with a relatively high positive voltage on the pulse lead 229 the switch is blocked and no signals are permitted to pass through,

VWhile only the left-hand portion of the circuit disclosed in Fig. 13 has been described in detail, it will be appreciated by one skilled in the art that the right-hand portion operates in exactly the same manner. 1n short, the input signal at lead 2|1 produces a corresponding output signal at lead 218.

As a result of the action of the fiip-op control circuit 226 acting on the double pole single throw switches 2|5, |48, the switch 2|5 is exclusively closed only during the first digit space. allowing one of the zero digit signals fromA the disk 200 to be applied to the carry input leads C, C' of the summing circuit. During the remainder of the digit spaces switch 2|5 is openand the carry delay circuit operates through switch |49 to apply a carry signal to the summing circuit as has been previously described. The summing of a given pair of binary numbers thus takes place independently of the sums taken immediately before or after. v

SUBTRAC'IION Subtraction is accomplished in a manner quite similar to addition. The primary difference is that instead of adding the first number to the second, the complement of the first number is added to the second number. Broadly this complement is obtained by inverting the signal of the subtrahend in order to reverse the sense of all of the couples which make up the number to be subtracted. In the present instance such reversal has been accomplished in the channel leading from the storage disk 20 by inclusion of the reversing switch 8|. In its simplest aspect this switch may be a simple manually operated double-pole double-throw toggle switch. Or, as will be apparent to one skilled in the art, an electromagnetic reversing switch or even an electronic reversing switch of conventionaldesign may be used. Where the computer disclosed herein is to be used as a larger and more complete calculating device, an electronic switch automatically controlled by a pulsed control line is preferred. Such an arrangement is disclosed in applicants copending application Ser. No. 76,088 filed February 12, 1949.

The eiect of operating the reversing switch in the present circuit is to substitute at the input terminals A, A' of the summing circuit l's for Os and 0s for ls. This gives the complement with respect to lll l1 or the largest number that the machine will hold. Actually. in order to obtain a correct result it is necessary to use the complement with respect to a number 1 greater than the capacity of the machine or 1000 00. The true complement is obtained in the practice of the present invention by adding 1 to the complement formed by inverting the signal. In accordance with the present invention this 1 is obtained from the same channel (associated with the zero generating disk 200) which is used to insert the initial 0 in the carry input leads C, C'. This is accomplished in the present instance by inserting they reversing switch 2|| in such channel preferably between the flip-flop circuit 204 and the zero control switch 2|5. The reversing switch 2|| is of the double-pole double-throw type and may be identical with the reversing switch 0| in the A, A leads and vto which` reference has previously been made. The reversing switch will cause an initial l rather than an initial 0 to be inserted in the carry leads when the summing circuit 82 operates upon the ilrst binary order. This in effect makes the complement 1 greater than it otherwise would be thus producing a true complement and causing the true difference to be written on the output disk |80.

acca-14s.,

DIGIT ADDBE USING MULTIGREJ TUBESr Aspfeviousiy covered, an. adder circuit is dis;- :ibsed` in Fig. Yl which produces. a carry `signal it its output when either. two or three 'of' the ijn- ;iut leads A, B, C are positive and which further produces a' write signal when either one, or lthree Ji' the input leads are positive. It 'will be 'apparentfto one skilled inthe thatv the invention is by meansV limited to the specific iircuit of Fig. l0 but includes alternative and quivalent circuits 'utilizing the sainebasic'teach- 'One such -alternative 'scheme has been set.

forth in Fig. 1.1fwit'n the input end output reads abeled 'Just asin Fig. 10..

ril-bes blased'ln accordance withjthe voltages ap- ?em'ing at the leads` A. B. C and A,. B, C. The irimary differencebetwe'en the. circuit. of Fig. 11

ma that. m rig. 1o previously "discussed 1s that nary control tubes.. In the case of each of the ubes the electrodes progressing outwardly from he cathode 'toward the plate may be designated |y the subscripts a-e inclusive.

To begin with -it will be helpful to observe he manner in which a 'carry signal is applied .t the output lead 65 when two or more of the nput leads A, B, C are positive. In the practice f the invention the three'nput leads A, B, C are listributed among the primary control tubes 2 40, #1,242 such that each of `such tubes iscontrolled 'y two of the input leads. In each instance the uppressorglrid connected directly to the cathde. tube 240 is controlled by lines B, C, 4| by lines A, C, and 242 by llines A,B. ABias kis from s battery orthe lik/e252 which lis huntedby a biafsadjusting potentiometer A254. bias is adjusted so that both Athe control and creen grids in one tube must be made posi-- tv'e before such tube passes plate current. With h1? one of the 'control Velectrodes positive 'the ub'e Aremains cut oif. In order vth'at 'the carry utput lead 85 maybe responsive 'to the state of ouduotlvity ot any one 'ofthe tubes 240, 24|, 242, ne cathode Vpotential l'of the tubes is caused to wing through a relatively wide range. This is Ifected bymeans ofa cathode resistor 255 which i common to all of the aboveementioned tubes. :1 eirect, therefore, the tubes 240, 24|, 242 "conzitate a cathode follower responsive to 'certa-'in ambinations of Vinput voltages.

'To prevent the control tubes from drawing rid current, grid resistors 256 are placed `in ariesy with vthe control grid ineach'instance AAs `result it has been found that `the control grids re never driven appreciably above cathode ipo'- intial. If fall three of the input leads A, B, C re made positive with respect tofground (corre- :onding to an inputof three binary ls) all three i the tubes are conductive. However, Vthe cathie-'resistor 255 preferably has a value such that hen one tube is conducting the voltage' drop :ross the tube is small as compared to the volt- ;e drop across the resistor 255. Thus, the` volt'- io drop the resistor and the voltage of output'. lead .'85 Awillbe substantially the mme; whether one, two or three tubes are conductim;` It is clear, then, that-this portion of the circuit fully meets the condition that a positive output signal be produced when either two or three of the input leads A, B, C are positive.

Attention will next tre-:given to the right-hand portion of Fig. 11 which 'applies a positive voltage to the write output leadi'l when either one or three of the input leads A, B, C are positive. lIt will be noted 'that the remaining rprimary control tubes are paired, thev cathodes of tubes 7243, and 245, 246 beingrespectivelyr `connected ftegether. The control electrodes of tubes 243 connected to leads C, B while those ofy tube-52" are connected to B, C'. The cathodes are confnected to a cathode resistor A258 which enables the cathode output lead 259 to swing :with spect to ground. With the circuit conneoted'las shown it will be apparent that the cathode-footprintV lead 2.59 will swing Vpositively onlywh'enftf,I B"v B, y'C' arev positive. `vIn terms of B fand 'C-alon'e, an output signal will be produced at 'the Vlead 1256 when either B or C are positive but not when both `are positive.

Reference may next be made to the secondary tube 250 having its screen 250 connected tothe output of tubes 243, 244. The control grid 25|)h is connected to the input terminal A". The tube 250, similar. to the other tubes in the .present embodiment, is connected as a cathode follower having; a cathode resistor 260. The write output lead 84 is connected directly to the cathode of this stage. Here again it .is necessary for both grids to be positive for plate current to flott. That is to say, it is necessary for A to be tive and for either B or C (but not both) to be positive. The latter condition, it will be recalled, is due to theV conductivity conditions set -up .for tubes 243, 244. In summary, therefore, conduction will take place in the secondary output. tube 2,56 producing a positive output signal on the write lead 64 when the following; Vcolmi-tionsl are` met:

Amillu AB-"minus C-nlus vIn-ordertol satisfy the remaining requirements, additional primary control tubes 245., 248 l"are feeding into secondary control tube 25|. ,y In the, case of tube 245 the grids are controlled by input lines B'., C while. the grids of tube 246 are conneeted to the input leads B, C. yThese tubes have a common cathode resistor 26| and are likewisebiased so that both of the .grids must be positive to produceconduction. The cathodes. are jointly connected to an output .lead 262. A positive sig,-A nal is applied to the latter output lead only when B and C are both positive or both negative. under such conditions a. positive voltageis ap.,- plied to the screen grid zeile.` cf the tube v'251. Thecontrol grid 25|b` on the otherhandisconnected directly to input line A. The cathode of this tube is directly connected to the Write output ,both positive or both negative..` lfhe twoseondi...

tions of conductivity may be summarized as follows:

A-plus B-minus C-minus A-plus B-plus C-plus Adding these two conditions to the two conditions previously set forth in connection with the secondary output tube 250 we see that a write signal is produced when either a single one of the input leads A, B, C is positive or when all three are positive. In terms of function, a binary 1 is Vwritten when either one or three binary 1's appear at the input.

In order that the parallel between the circuit described immediately above and that previously discussed may be more clearly drawn, a table of over-al1 operating characteristics may be set up which corresponds generally to Table I as follows:

yALTERNATIVE DIGIT ADDER CIRCUIT USING DIODE RECTIFIERS In accordance with one of the more detailed aspects of the invention another alternative adder circuit using unidirectional electronic devices is the form of diodes instead of grid controlled rectiilers is disclosed in Fig. 12. The wave forms applicable to the circuit of Fig. 12 are to be found in Fig. 12a.

Just as in the case ofthe previous two summing circuits (Figs. l and 11) input leads A, B, C are provided on which are respectively received couples corresponding to rst and second data' signals together with a carry signal all representative of binary digits. The inverse or comple- Table II= Tube Tube Tube Tube Tube Tube Tube Tube 250 Tube 251 Write Carry Iads, pOStiVe 240 241 242 243 .4 244 245 246 (it-243, (r-245, Out- 011t- (B-C) (AC) (A-B) (C-B) (CB) (CB') (C-B) 1 244) 246) Put Put.

. x C C C C C i Z C C C minus. minus c c e c c z o c z plus... D6. C C C C Z C C Z C do. D0. C C C Z C C C Z C do. D0. C C Z C Z C C C C minus, plus. C Z C Z C C C C C d0 D0. Z C C C C C Z C C do. Dc. Z Z Z C C C Z C Z Vplus Dc.

C-Cut-o. Z-Conducting.

The letters in parenthesis directly under the tube numbers for tubes 243-246 indicate the leads which supply the grids of that particular tube. The characters directly under tubes 250 and 25| indicate that the input lead A or A must be a plus voltage and, in addition, certain tubes as indicated must be conducting. It will be seen that the signals on the write and carry leads as listed at the right-hand portion of the table correspond exactly to the conditions listed in Table I.

The alternative scheme of Fig. l1 is merely representative of the various forms the circuit may take without departing from my basic teachings. If desired. a portion of the tubes may be of the multigrid variety while the remainder may be simple triodes. For example the tubes in the left-hand portion of Fig. 11 indicated at 240, 24|, 242 may be replaced by a pair of triodes connected as shown at 86, 81 in Fig. 10. In the latter event it will, of course, not be necessary to connect the plate terminal to the resistor H5 shown in the latter figure. Nor is the invention limited to the use of tubes having two control grids since it will be obvious to one skilled in the art that the teachings are applicable to tubes other than rec'eiving type tetrodes. One important factor is that there bea bank of tubes employed as primary control tubes and excited directly from the input lines together with a bank of secondary control tubes which are controlled in accordance with the state of conductivity of the primary control tubes. Also a significant feature common to the circuits of Figs. and 11 is the use of the inverted as well as the direct input signal for controlling the primary control tubes.

Fig. 11a shows the voltages existing at four signicant points in the circuit of Fig. 11. namementary signals are, as before, received on the respective primed input leads designated A', B', C'. The output leads of the circuit of Fig. 12 comprise a write lead 84 and a carry lead 85. Combinations of the instantaneous potentials on the six input leads are eiective, through the disclosed circuit, to produce a desired voltage condition on the write lead when one or three of the leads A, B, C are positive and to produce the desired condition on the carry lead only when two or three of the leads A, B, C are positive.

Referring to the circuit of Fig. 12 for accomplishing the above it will be seen that two banks of rectifiers are employed. The rst bank 35i consists of what may be termed primary rectiers connected in groups of three to terminals 352 to 358 inclusive. These rectiers are connected in the various possible combinations to the input leads A. B, C and A. B. C. For purposes of convenience each has been designated by a reference numeral corresponding to the terminal and line to which it is connected. For example, the first rectifier is designated 352A to indicate that it is connected between the terminal 352 and the line A.

Each of the terminals 352-358 inclusive is grounded through a resistor, such resistors being designated 362 to 368 inclusive. The magnitude of the resistance is preferably high as compared to the forward resistance of the rectiers. The rectifiers themselves may consist of crystals oi germanium commercially designated 1N34. Ii desired, however, such rectiflers may be formed of other materials having a backward resistance which is high as compared to the forward resistance and may even consist of vacuum tube rectiers such as one-half of a type 6H6 vacuum tube The operation oi' the circuit thus far described will bemade'clear by 'considering what occurs in the group 'of rectiers at the left-hand portion of Fig. 12 under various conditions of Aapplied line voltage. It will be noted that the rectifers are respectively connected to 'input lines A, B' and C'. Ifany o! these 4lines should atany given instant be positive, current will ow through its associated rectier, through the series resistor 882. to ground. Since the Yseries resistor is of relatively high resistance, the output terminal 852 of the rectiers during current flow will as- 'mme-a potential which is substantially equal to thepositive line potential. If, on the other hand, the instantaneous value of the .voltages on the ,lines A. B',C' are all negative, then no current will ilow through 'any of the rectiers and the rectier output terminal 352 will be substantially at ground potential. Thus, in the case of the rilt group of rectiers the condition which must he met in order to have terminal 352 near ground potential is to have a negative voltage on line A and positive voltages on lines B and C.

The remainder of the rectier groups and the associated resistors operate in the same manner except 4that they are connected to different combinations of the six input terminals. i Just as in the case of the rst group of rectiers, a certain combination of voltages on the input leads will Acause the output terminal to be near ground po- Y tential. It will be seen that there is only one condition ot the input lines which will cause each of the terminals 352-358 to be near ground potential.A Such conditions are summarized in the fol- .lowin table:

Table III Voltage Condition of Lines A, B, C, to Cause Terminal to be elar Ground Poten- Number of Input Leads A,

which Are Positive Terminal In the practice oi' the invention. the output voltages of the rectiflers obtained at terminals '352-358 are divided for feeding into circuits associated with the write output lead 84 and the .carry output lead 85. Such division is accomplished in a manner such that a predetermined output voltage exists on the Write lead 84 when either one or three of the input leads A, B, C are .positive and further, so that a predetermined output' voltage exists on the carry lead 85 when either two or three of the input leads A, B, C are positive. From the above table, it will be apparent .that to satisiy this condition terminals 352-354 should be associated in one group and -terminals 356-358 formed into a second group. Terminal 355, which is near ground potential wheny the leads A, B, C arev all positive, is ineluded with each of the groups since this condition requires both writing and carrying.

In order .that predetermined voltage conditions at the terminals 352-358 may cause a signal to appear on. the appropriate output line and in order to isolate the output lines against undesired voltage conditions, an additional bank of secondary rectiers is used. Thus terminals 352-355 are connected to the carry output-lead through rectiers 312-315 and terminals 355-358 are connected to the write lead 84 through rectiers 31E-319. So that the voltage on the carry output lead 85 might swing between predetermined limits, the line is connected to za source of potential 384 through a series resistor 385. Correspondingly, the output lead 84 is connected to the source of potential v384 through .a series resistor 386. In operation, the existence of a positive potential at one of the rectifier terminals, for example terminal 352, causes a iiow of current to ground through the associated resistor, here 352. Since the resistance of the series resistor 382 is high, the terminal 352 asf sumes ra positive potential substantially that o1 the positive line to which it -is connected. With the terminal 352 positive there is no effect whatsoever on the associated output lead since the rectifier 312 is so polarized as vto performan isolating function.

Preferably, theresistors 385,385 are of a high resistance ascompared to the resistors'362-368. For example, in a practical embodiment the-resistors 385, 388 may be approximately one megohm while the resistors 362-368 vare on the order of 100,000 ohms. The voltage of the-p0 tential source 384 is so adjusted that with.f.all of the terminals 352-358positive,fno current will flow through the resistors 385, 388. Under such circumstances the voltage existing at the output leads 84, 85 will be substantially the same as that ofY the potential source 384.-

The voltage on the output leads changes "markedly, however, when one of the associated rectifier terminals, for 'example terminal 352, is reduced to substantially ground potential. The latter can be clearly seen by noting the path of current ow with terminal 352 at ground potential. The circuit under such circumstancesincludes the potential source 384, the series resistor 385, the rectifier 312, and the resistor-382. Due to the fact that the resistor 385 is large'a's compared to the resistor 352, most-of the voltage drop will occur across the resistor 385 thereby reducing the potential on the output lead 85 substantially to ground potential. The potential on the lead 85 is reduced to near ground potential in exactly the same manner whenever the potential at any one of the terminals 353-355 is correspondingly reduced. In short, the voltage on the carry output lead 85 is reduced to substantially ground potential whenever two or three of the input leads A, B, C are positive. This condition, occurring during the rs't half of a digit space in the present circuit, causes a binary 1 vto be inserted in the summation of the next higher order. The right-hand portion voi the circuit operates in similar fashion: Whenever any one of the terminals 355-358 is reduced to ground potential, the voltage at the output leal 84 is reduced to substantially ground Apotential. When this condition obtains during the rst half of a digit space, a write 1 signal is produced at the output lead 84.

Comparing this circuit to the-other two alternative circuits disclosed in Figs. 10 .and 11 it will be noted that the voltages produced at the output leads 84, 85 are just the reverse of those previously obtained. That is to say, zero output voltages are obtained on the write and carry leads for conditions which produced positive voltages in the previous circuits. This state of aiairs, however, is readily compensated for merely by .interchanging the direct and reverse 

